1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including an input/output circuit having a complementary metal oxide semiconductor (CMOS) structure and, more particularly, to an. input/output circuit that facilitates input/output interfacing with a device that operates at different power supply voltages.
2. Description of the Related Art
The recent advances in the technology of semiconductor integrated circuit devices such as IC and LSI devices greatly depend on element miniaturization represented by scaling. In the old generation of elements having a line width of 1 .mu.m or more, only element dimensions are scaled, whereas the power supply voltage remains at 5 V. In the submicron generation, however, it is becoming difficult to maintain a power supply voltage of 5 V. That is, a decrease in breakdown voltage with a reduction in gate oxide film thickness or a decrease in hot carrier breakdown voltage with a reduction in gate length cannot be neglected. On the other hand, an increase in current consumption with an increase in the number of elements per chip conflicts with the demand for lower power consumption required by portable devices. As described above, from the point of view of elements and users, demands have arisen for lower power supply voltages. In reality, however, the shift of a power supply voltage to 3 V is not smoothly made. This is because if all the ICs of a given system are to be designed to operate at 3 V, some ICs, represented by analog ICs, are not suitable for a reduction in power supply voltage. For this reason, a system including both 3-V and 5-V circuits is inevitably required besides an "all 3-V" system. The present invention is related to interfacing between integrated circuits using different power supply voltages. More specifically, the present invention is applied to integrated circuit devices, such as a microcomputer, a memory, a general-purpose logic, and an ASICLSI, which demand a reduction in power supply voltage.
FIG. 1 shows an input/output circuit normally used for a semiconductor integrated circuit device. In general, an input/output circuit of an integrated circuit (LSI) having a CMOS structure is constituted by a CMOS circuit as in the case of an internal circuit element of the integrated circuit. The input/output circuit includes an output buffer 2 and an input buffer 3, both of which are connected to an input/output terminal 1. The input/output terminal 1 is called a pad on the semiconductor substrate. Such pads are formed on a peripheral portion of the semiconductor substrate. A protective circuit against an externally caused electrostatic discharge is connected between these buffers and the input/output terminal 1. This protective circuit includes a resistor R1 and a diode D1. The output buffer 2 is constituted by an n-channel MOSFET (to be referred to as an NMOS transistor hereinafter) Q1 and a p-channel MOSFET (to be referred to as a PMOS transistor hereinafter) Q2. The input buffer 3 is constituted by an NMOS transistor Q3 and a PMOS transistor Q4. Signals are applied from the transistors Q3 and Q4 to the LSI. Signals A and B from the LSI are respectively applied to the PMOS and NMOS transistor Q2 and Q1 of the output buffer 2. The input/output states of the input/output circuit are shown in the following Table 1:
TABLE 1 ______________________________________ A B Q1 Q2 Input/Output State ______________________________________ L L off on H-level output state H H on ff L-level output state H L off off high-impedance input state ______________________________________
The input/output circuit operates in the following three input/output states. When both the signals A and B are at L level (Low Level), the NMOS transistor Q1 is turned off, and the PMOS transistor Q2 is turned on. As a result, the input/output state of the input/output circuit becomes an H (High)-level output state. When both the signals A and B are at H level (High Level), the transistor Q1 is turned on, and the transistor Q2 is turned off. As a result, the input/output state becomes an L (Low)-level output state. When the signals A and B are at H level and L level, respectively, both the transistors Q1 and Q2 are turned off, the input/output state becomes a high-impedance input state.
The input/output circuit constituted by such a CMOS circuit is widely used for semiconductor integrated circuit devices. However, a voltage lower than a ground potential of 0 V or higher than a power supply voltage Vcc cannot be applied to the input/output terminal 1. If, for example, a voltage exceeding the voltage Vcc is applied to the input/output terminal 1, the p-n junction formed in the drain area of the PMOS transistor Q2 is biased in the forward direction. As a result, a large current flows from the input/output terminal 1 to a power supply Vcc. For this reason, the rated voltage applied to the input/output terminal 1 is generally limited within the range of ground voltage of 0 V+0.5 V (inclusive) to power supply voltage Vcc+0.5 V (inclusive).
However, with the advances in the miniaturization of an integrated circuit having a CMOS structure and an increase in integration degree, it is becoming difficult to conform to such limitations. For a CMOS-LSI using MOS transistors having a gate length of 0.5 .mu.m or less, it is proposed that the power supply voltage, i.e., 5 V, which has been conventionally used, be decreased to nearly 3 V, in order to prevent a deterioration in element reliability due to an increase in the strength of an electric field in an internal element. In addition, a decrease in power supply voltage, i.e., a decrease in signal amplitude, is preferable in terms of prevention of noise in input/output switching of an integrated circuit. CMOS circuits are not used alone in an integrated circuit but are connected to other CMOS-LSIs having various functions to constitute a system. However, it is not assumed that all these CMOS-LSIs operate at a low power supply voltage, and a plurality of integrated circuits having power supply voltages of 3 V and 5 V may constitute a system. Therefore, a voltage of 5 V may be applied, as an H-level input, to an input/output circuit of an integrated circuit having a power supply voltage of 3 V. In this case, as described above, since a forward bias to the p-n junction is generated, a conventional input/output circuit cannot be used directly. This forward p-n junction current may destroy an element.
Conventional master slice type semiconductor integrated circuit devices formed on p-type silicon semiconductor substrates will be described below with reference to FIGS. 2 to 8. FIG. 2 is a plan view of a p-type silicon semiconductor substrate 10. FIG. 3 is an enlarged plan view of a region R in FIG. 2. The region R includes two regions R1 and R2, each having one output buffer formed therein. An n-well 11 used for an input/output circuit is formed on a peripheral portion of the semiconductor substrate 10. This n-well 11 is formed along the respective sides of the substrate 10 to have an annular shape. A plurality of input/output terminals (pads) 1 are formed in a line between the n-well 11 and each side so as to allow a main logic circuit formed in the semiconductor substrate 10 to be electrically connected to an external circuit through the input/output circuit. The semiconductor substrate 10 is connected to the ground potential. Each gate 19 is made of polysilicon. The entire n-well 11 formed on the p-type semiconductor substrate 10 is connected to the same potential (e.g., 5 V). For this reason, external signals corresponding to a plurality of voltage levels are interfaced by using an A1 wiring pattern 12 as an overlying layer as needed. Furthermore, in such a case, only the potential of the source of a PMOS transistor in the n-well 11 is changed. FIG. 3 is a schematic view of a conventional input/output circuit pattern for obtaining two types of outputs, i.e., a 5-V level output Z1 and a 3-V level output Z2, when the n-well 11 is biased at 5 V. FIG. 4 is a circuit diagram of a 3-V level output buffer 2 for this circuit.
At this time, the source of a PMOS transistor P12 is biased at 3 V to obtain a 3-V level output. When an input A2 for a 3-V level output changes to L level (0 V), the PMOS transistor P12 is turned on. As a result, a potential of 3 V is obtained at the output Z2. In this case, however, since the PMOS transistor P12 is formed in the n-well 11 together with another PMOS transistor P11, a back gate voltage of 5 V is commonly applied to the two transistors, resulting in a deterioration in transistor characteristics, e.g., a decrease in speed.
In an integrated circuit incorporating input protection diodes D2 and D3 shown in FIG. 8 since the cathode side of the protection diode D2 is common to an n-well, if the integrated circuit operates at 3 V, a current flows in the circuit through the protection diode D2 on the positive side upon application of a 5 V level input signal. Therefore, such a circuit cannot be used for a system designed to suppress power consumption. In the above-described prior art, since transistors having different voltage levels are formed in one well region, the output voltage level can be changed only by changing the source voltage, resulting in a decrease in speed. In order to prevent such a deterioration in the transistor characteristics of an input/output circuit, the master slice type semiconductor integrated circuit device shown in FIG. 5 has been proposed.
In this device, independent n-wells are formed along the respective sides. A change in potential is performed by two n-wells 113 formed along adjacent sides and connected to a potential of 5 V, and two n-wells 114 formed along adjacent sides and connected to a potential of 3 V. A decrease in speed due to a back gate effect is prevented in such a manner that the n-wells for interfacing circuits at 5 V are biased at 5 V, and the n-wells for interfacing the circuits at 3 V are biased at 3 V. Since a plurality of input/output circuits as units are formed in one n-well region, a pitch d of the pads 1 is decreased, as shown in FIG. 6. FIG. 6 is a plan view showing a portion of an input/output circuit region of the semiconductor integrated circuit device. As is apparent from FIG. 6, however, in this structure, the formation regions of 5-V and 3-V input/output circuits are limited to the respective sides. That input/output circuits cannot be freely arranged is a critical disadvantage to a master slice type semiconductor integrated circuit device. Therefore, as shown in FIG. 7, it is proposed that n-wells be formed in units of input/output circuits. FIG. 7 is a plan view showing a region, of another conventional master slice type semiconductor integrated circuit device, which corresponds to the portion shown in FIG. 5. With this structure, signals having a plurality of levels can be interfaced by biasing special n-wells at the respective interfacing levels.
In this structure, however, since the input/output circuit formation regions must be formed at predetermined intervals, a pad pitch D shown in FIG. 7 is inevitably larger than the pad pitch d shown in FIG. 6. Consequently, the number of pins is greatly decreased, while the chip size is increased. As described above, if the conventional master slice type integrated circuits are used for a system including integrated circuits having a plurality of voltage levels, it is 10 difficult to perform interfacing with satisfactory characteristics.